
CAV24C02, CAV24C04, CAV24C08, CAV24C16
SCL
SDA
8 th Bit
Byte n
ACK
t WR
STOP
CONDITION
Figure 7. Write Cycle Timing
START
CONDITION
ADDRESS
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
S
P
SLAVE
n=1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P v 15
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
SDA
a7
a0
d7
d0
t SU:WP
WP
t HD:WP
Figure 9. WP Timing
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